Banca de DEFESA: ALVARO MEDEIROS AVELINO

Uma banca de DEFESA de DOUTORADO foi cadastrada pelo programa.
DISCENTE : ALVARO MEDEIROS AVELINO
DATA : 09/06/2017
HORA: 09:00
LOCAL: Auditório do nPITI
TÍTULO:

LP-P2IP: A low power consumption P2IP implementation using FPGA partial reconfiguration.

PALAVRAS-CHAVES:

Keywords: FPGA, Dynamic Partial Reconfiguration, video processing, real time.

PÁGINAS: 52
GRANDE ÁREA: Engenharias
ÁREA: Engenharia Elétrica
SUBÁREA: Circuitos Elétricos, Magnéticos e Eletrônicos
ESPECIALIDADE: Circuitos Eletrônicos
RESUMO:

This work uses as its basis the P2IP architecture, which consists of a coarse grain
reconfigurable (runtime) architecture with low latency, applied to real time image processing.
This architecture has been validated in FPGA (Possa 2013), being implemented
with some basic image processing algorithms, such as Canny Edge Detection and Harris
Corner Detection. The aim of the present work is to enlarge the architecture functionality
through Dynamic Partial Reconfiguration, which consists in dividing the chip area in two
regions: a static and a dynamic one. The latter can be reprogrammed without resetting
the whole system. It leads to a lower dynamic energy consumption, a relevant feature if
the system is battery powered. The variables that will be used to validate the system are
the consumption, latency and maximum operating frequency.

MEMBROS DA BANCA:
Presidente - 1837410 - VALENTIN OBAC RODA
Externo ao Programa - 347065 - JOSE ALBERTO NICOLAU DE OLIVEIRA
Externo ao Programa - 2244846 - JULIO CESAR PAULINO DE MELO
Externo à Instituição - CARLOS ALBERTO VALDERRAMA SAKUYAMA - UMONS
Externo à Instituição - EDUARDO MARQUES - USP
Externo à Instituição - EMERSON CARLOS PEDRINO - UFSCAR