Banca de DEFESA: JOSÉ BATISTA DE SALES FILHO

Uma banca de DEFESA de MESTRADO foi cadastrada pelo programa.
DISCENTE : JOSÉ BATISTA DE SALES FILHO
DATA : 14/10/2016
HORA: 09:30
LOCAL: Sala 101 nPITI
TÍTULO:

Integrated circuit signal conditioning for wire-mesh sensors applied to the monitoring of multiphase flows

PALAVRAS-CHAVES:

complex impedance measurement, multiphase flow, wire-mesh sensors, CMOS integrated circuits

PÁGINAS: 80
GRANDE ÁREA: Engenharias
ÁREA: Engenharia Elétrica
SUBÁREA: Circuitos Elétricos, Magnéticos e Eletrônicos
ESPECIALIDADE: Circuitos Eletrônicos
RESUMO:

In many petrochemical and nuclear industry applications, monitoring of streaming oil-gas-mixtures (multiphase flows) has been motivating the development of investigation methods based on tomographic imaging. Some investigated phenomena, such as gas bubble propagation, feature fast-changing dynamics, thus demanding a good time resolution for monitoring systems. In order to achieve faster imaging methods compared to established tomographic techniques, wire-mesh sensors were developed over the last decade. These sensors, which are inserted inside pipelines, are composed of an electrode mesh that performs fluid complex impedance measurements. Despite their intrusive nature, multiphase flow images can be generated without iterative reconstruction algorithms.

It is proposed in this work an integrated circuit (IC) to perform a 4x4 wire-mesh sensor signal conditioning, applied to phase fraction calculations of multiphase flows. The circuit integration reduce both size and energy consumption of the conditioning circuits, in comparison with established systems which use discrete components.

The chip comprises the following blocks: a transimpedance amplifier that converts the sensor output currents into voltage signals; a phase syncronous demodulator, which provides in-phase and quadrature voltage signals that are functions of the main fluid electrical parameters (permittivity and conductivity); and a low-pass filter, prior to the off-chip analog-to-digital conversion.

The circuit was designed for a 130-nm standard CMOS technology. The IC validation is performed via post-layout simulations.

MEMBROS DA BANCA:
Presidente - 2140683 - DIOMADSON RODRIGUES BELFORT
Interno - 1149567 - ANDRES ORTIZ SALAZAR
Interno - 1284113 - SEBASTIAN YURI CAVALCANTI CATUNDA
Externo à Instituição - ANTONIO AUGUSTO LISBOA DE SOUZA - UFPB